Pre-Grant Publication Number: 20070174746
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Prior Art Detail
Summary / Description
| Summary / Description | A codesign methodology incorporates timing speculation into a low-power micropocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths |
Basic Information
| Type of Prior Art | Print Publication |
| Publication Title * | Computer |
| Author | Austin, Todd et al. |
| ISBN | |
| Page Range | 57 - 65 |
| Medium | Journal article |
| Publication Date * | March 2004 |
| URL | |
Notes / To Do
| Notes | |
Excerpt
Excerpt Self-tuning systems:
In its current form, Razor sets voltage globally—
chip-wide, but we could refine it to allow distributed voltage control. Under a distributed control system, each processor pipeline stage could operate at a separate, potentially different voltage determined by monitoring pipeline stage error rates. Releasing the constraint of a single operating voltage enables significant optimizations
of voltage assignments across the processor stages, leading to further power savings.
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Claims
1
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Figures 2 and 3 show a plurality of processors operating in lockstep with error rates determined manually as a function of voltage. Page 63 teaches that the voltages of multiple parallel processors could be individually tuned based on a monitored error rate.
Figures 2 and 3 show a plurality of processors operating in lockstep with error rates determined manually as a function of voltage. Page 63 teaches that the voltages of multiple parallel processors could be individually tuned based on a monitored error rate.
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2
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Figure 2 shows voltages ranged from low error rates to 100% error rates.
Figure 2 shows voltages ranged from low error rates to 100% error rates.
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8
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See claim 1
See claim 1
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14
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See claim 1
See claim 1
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