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Pre-Grant Publication Number: 20090106489

Data processing apparatus with shadow register and method thereof

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Prior Art Detail

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#522US20040143613A1: Floating point bypass register to resolve data dependencies in pipelined instruction sequences

Applies to Claims 1,2,7,8

Submitted by: Diane WillisLast updated: almost 4 years ago

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Summary / Description

Summary / Description

..having a register array..plurality of operands, a pipeline for executing..instructions with a plurality of stages, ..having a stage register, data input registers..(which) form the first stage register of the pipeline. An input port loads..into one..data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port,and the output..provided to the data input registers, such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers from a respective bypass-register...

Basic Information

Type of Prior Art	Issued Patents - US

Country	United States of America

Patent/Application #	20040143613

Kind Code	United States (US) - United STATES Patent - A

Patentee Name	International Business Machines Corporation

Relevant Pages, Columns, or Lines	[0012] - [0016]

URL

Filing Date	January 7, 2004

Additional Information

Notes / To Do

Notes	Prior art suggested by John E. Campbell, IBM, and entered by Diane Willis.

Excerpt

Excerpt

According to the broadest aspect of the present invention a floating point unit of an in-order-processor is disclosed having: a register array for storing a plurality of operands, a pipeline for performing floating point instructions with a plurality of stages, each stage having a stage register, data input registers for keeping operands to be processed, whereby said data input registers form the first stage register of said pipeline, and an input port for loading operands from outside said floating point unit into one of said data input registers, which is characterized by comprising: a plurality of bypass-registers, the input of which is connected to said input port, and the output of which is provided to said data input registers, such that data propagating through the pipeline to be loaded into said register array can be immediately supplied to one or more particular data input register from a respective bypass-register without a delay caused by additional pipeline stages to be propagated through and passing them back from the end of the pipeline. By the term “bypass-register” set the idea to be understood is that the pipeline is bypassed for data which is stored in said register set. The data concerned is the operand data associated with a LOAD instruction. In other words, the main goal of the present invention, to resolve the wiring congestion of the unit is achieved now within the bypass-register. The plurality of bypass registers is advantageously operated in a FIFO (‘First In First Out’—a way of stack-organization) manner. If the same number of bypass-registers is provided as pipeline stages are present, each individual operand from each individual pipeline stage may advantageously be fed back from the bypass-registers provided by the invention. If further the bypass-register set is implemented as a sub-portion of the register array which is always present in a floating point unit anyway, the same multiplexer logic may be advantageously used for the register array and for the bypass-register set of this invention. This saves chip area in contrast to a solution in which the bypass-registers, provided by the present invention are implemented separately from the register array.

Relevance

Claims

A data processing apparatus, comprising:a register bank, comprising a plurality of registers respectively for storing a plurality of operands, the registers comprising a first register, the operands comprising a first operand, wherein the registers are n-bit registers, wherein n is a nature number;

a shadow register, for storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register; and

an operation unit, for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command.

Relevance

See the Abstract (in the Summary/Description of this prior art information) and the Excerpt.

Claim Chart

All

The data processing apparatus according to Claim 1, wherein the registers further comprises a second register, and the data processing apparatus further comprises:a logic unit, for providing the operational data of the first register to the second register in response to a second control signal, and then providing the first backup operand stored in the shadow register to the first register.

Relevance

See Claim 1.

Claim Chart

All

A data processing method, comprising:providing a register bank comprising a plurality of registers for respectively storing a plurality of operands, wherein the registers comprises a first register, the operands comprising a first operand;

storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register;

performing at least an arithmetic operation on the operands to obtain an operational data in response to an arithmetic operation command; and

storing the operational data in the first register.

Relevance

See Claim 1.

Claim Chart

All

The data processing method according to Claim 7, wherein the registers comprises a second register, and the data processing method further comprises:storing the operational data in the second register in response to a second control signal; and

storing the first backup operand in the first register.

Relevance

See Claim 1.

Claim Chart

All

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