Pre-Grant Publication Number: 20090106489
Data processing apparatus with shadow register and method thereof
Please help the USPTO examine the application by evaluating the relevance of the publicly submitted prior art to the patent application. Peer To Patent forwards the Top 10 most relevant prior art submissions and their annotations to the USPTO.

Review this prior art and click on the thumbs up (or down) to indicate whether this submission should be forwarded to the USPTO.
If you login then you can add an annotation by typing in the box at the bottom of the screen to comment on the relevance of the prior art to the claims of the patent application.
Prior Art Detail
Annotations(0)
#520Design of the IBM RISC System/6000 floating-point execution unit
Applies to Claims 1,2,5,7
Submitted by: Diane WillisLast updated: almost 4 years ago
0 thumbs up 0 thumbs down
Summary / Description
Summary / DescriptionArticle describing a multiply-add-fused (MAF) unit.
 
Basic Information
Type of Prior ArtPrint Publication
 
Publication Title *IBM Journal of Research and Development
 
AuthorR. K. Montoye E. Hokenek S. L. Runyon
 
ISBN
 
Page Range59-70
 
MediumJournal article
 
Publication Date *January 1990
 
URL
 
Notes / To Do
NotesSubmitted on behalf of Eric Schwarz, IBM, by Diane Willis.
 
Excerpt
Excerpt
The key feature of the FPU (floating point unit) is a unified floating-point multiply-add-fused unit (MAF) which performs the accumulate operation (A x B) + C as an indivisible operation. This single functional unit reduces the latency for chained floating-point operations, as well as rounding errors and chip busing. It also reduces the number of adders/normalizers by combining the addition required for fast multiplication with accumulation. The MAF unit is made practical by a unique fast-shifter, which eases the overlap of multiplication and addition, and a leading-zero/one anticipator, which eases overlap of normalization and addition. The accumulate instruction required by this architecture reduces the instruction path length by combining two instructions into one.
 
Relevance
Claims
1
A data processing apparatus, comprising:a register bank, comprising a plurality of registers respectively for storing a plurality of operands, the registers comprising a first register, the operands comprising a first operand, wherein the registers are n-bit registers, wherein n is a nature number;a shadow register, for storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register; andan operation unit, for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command.
Relevance
It seems a fused multiply-add operation is being claimed, which is similar to the IBM RS/6000 in 1990 in the reference. If what is being claimed is a fixed-point multiply-accumulator, a fixed-point multiply-accumulator is even older.
It seems a fused multiply-add operation is being claimed, which is similar to the IBM RS/6000 in 1990 in the reference. If what is being claimed is a fixed-point multiply-accumulator, a fixed-point multiply-accumulator is even older.
Claim Chart
All
2
The data processing apparatus according to Claim 1, wherein the registers further comprises a second register, and the data processing apparatus further comprises:a logic unit, for providing the operational data of the first register to the second register in response to a second control signal, and then providing the first backup operand stored in the shadow register to the first register.
Relevance
See Claim 1.
See Claim 1.
Claim Chart
All
5
The data processing apparatus according to Claim 1, wherein the arithmetic operation command is a multiply-accumulate (MLA) command, and the operation unit performs at least a multiplying-operation and at least an accumulating-operation on the operands.
Relevance
See Claim 1.
See Claim 1.
Claim Chart
All
7
A data processing method, comprising:providing a register bank comprising a plurality of registers for respectively storing a plurality of operands, wherein the registers comprises a first register, the operands comprising a first operand;storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register;performing at least an arithmetic operation on the operands to obtain an operational data in response to an arithmetic operation command; andstoring the operational data in the first register.
Relevance
See Claim 1.
See Claim 1.
Claim Chart
All
0 days left
Activity
Application
Discussion (0)
Prior Art (3)
Research (0)
Subscribe to this Community
Invite a Reviewer
HOW TO USE PEER TO PATENT
Peer To Patent Videos