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Pre-Grant Publication Number: 20090106489

Data processing apparatus with shadow register and method thereof

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Prior Art Detail

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#519US4969118: Floating point unit for calculating A=XY+Z having simultaneous multiply and add

Applies to Claims 1,2,5,7

Submitted by: Diane WillisLast updated: almost 4 years ago

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Summary / Description

Summary / Description	Processor floating point unit - provides for simultaneous multiply and add operations

Basic Information

Type of Prior Art	Issued Patents - US

Country	United States of America

Patent/Application #	4969118

Kind Code	United States (US) - United STATES Patent - A

Patentee Name	International Business Machines Corporation

Relevant Pages, Columns, or Lines	Col. 1, Lines 30-40; Col. 2 Li

URL

Filing Date	January 13, 1939

Additional Information

Notes / To Do

Notes	Submitted on behalf of Eric Schwarz, IBM, by Diane Willis.

Excerpt

Excerpt

A single floating point that produces the result A×B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors. Since it is always useful to maximize the speed with which a floating point processor performs its functions, one known technique used to obtain performance gains is to provide specialized hardware to implement specific floating point functions. For example, certain combinations of arithmetic functions occur regularly in computations. The present invention is directed to an apparatus for use in a floating point processor optimized for the computation of expressions of the form A×B+C. It is thus an object of the invention to provide a single hardware structure capable of producing the operation of A×B+C, where A, B and C are floating point numbers.

Relevance

Claims

A data processing apparatus, comprising:a register bank, comprising a plurality of registers respectively for storing a plurality of operands, the registers comprising a first register, the operands comprising a first operand, wherein the registers are n-bit registers, wherein n is a nature number;

a shadow register, for storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register; and

an operation unit, for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command.

Relevance

It seems what is being claimed is a simple ALU (arithmetic logic unit) design. (Col. 3, Lines 29 - 35). The term "shadow register" is very common and has been used for many years. Copying a register to a shadow register and performing an operation on it sounds like a simple ALU.

Claim Chart

All

The data processing apparatus according to Claim 1, wherein the registers further comprises a second register, and the data processing apparatus further comprises:a logic unit, for providing the operational data of the first register to the second register in response to a second control signal, and then providing the first backup operand stored in the shadow register to the first register.

Relevance

See Claim 1.

Claim Chart

All

The data processing apparatus according to Claim 1, wherein the arithmetic operation command is a multiply-accumulate (MLA) command, and the operation unit performs at least a multiplying-operation and at least an accumulating-operation on the operands.

Relevance

See Col. 2, Lines 12-20.

Claim Chart

All

A data processing method, comprising:providing a register bank comprising a plurality of registers for respectively storing a plurality of operands, wherein the registers comprises a first register, the operands comprising a first operand;

storing a first backup operand for making a backup of the first operand in response to a first control signal, wherein the first operand is stored in the first register;

performing at least an arithmetic operation on the operands to obtain an operational data in response to an arithmetic operation command; and

storing the operational data in the first register.

Relevance

See Claim 1.

Claim Chart

All

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