Pre-Grant Publication Number: 20080016013
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Prior Art Detail
Summary / Description
| Summary / Description | This paper is one of many (do a Google on "fpga fitness function" for more) that describes the use of a programmable hardware device (fpga) for fitness evaluation in a genetic algorithm. |
Basic Information
| Type of Prior Art | Print Publication |
| Publication Title * | Genetic Programming and Evolvable Machines, Volume 2 |
| Author | Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo a |
| ISBN | |
| Page Range | 33-60 |
| Medium | Journal article |
| Publication Date * | March 2001 |
| URL | http://portal.acm.org/citation.... |
Notes / To Do
| Notes | |
Excerpt
Excerpt Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row * 520-column set covering problem
2,200* faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320* faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600* for the 36-residue protein folding problem. |
Relevance
Claims
1
Relevance
The use of a programmable hardware device (i.e., an FPGA) for fitness evaluation is explicitly described.
The use of a programmable hardware device (i.e., an FPGA) for fitness evaluation is explicitly described.
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2
Relevance
The use of an FPGA for fitness evaluation is explicitly described.
The use of an FPGA for fitness evaluation is explicitly described.
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12
Relevance
The method described in the paper includes the use of a programmable hardware device (an FPGA) for fitness evaluation.
The method described in the paper includes the use of a programmable hardware device (an FPGA) for fitness evaluation.
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13
Relevance
The method described in the paper includes the use of an FPGA for fitness evaluation.
The method described in the paper includes the use of an FPGA for fitness evaluation.
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