Pre-Grant Publication Number: 20110191092
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Prior Art Detail
Summary / Description
| Summary / Description | An integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation backplane. |
Basic Information
| Type of Prior Art | Print Publication |
| Publication Title * | Symphony: A Simulation Backplane for Parallel Mixed-Mode CO-Simulation of WLSI Systems |
| Author | Antonio R.W. Todesco and Teresa H.-Y. Meng |
| ISBN | |
| Page Range | |
| Medium | Journal article |
| Publication Date * | 1996 |
| URL | |
Notes / To Do
| Notes | |
Excerpt
Excerpt The last several years have seen a steady growth in the complexity
of IC and system integration. As a consequence, there is a need for
longer, larger and more realistic simulations performed within a
fin] the design-to-market time. Usually multiple simulators are used
in 1 he design pass because no single simulator addresses all modeling,
performance and verification issues.
Multi-level mixed-mode co-simulation has a great potential to efficiently
simulate large systems containing both digital and analog
components, with portions of the system described at different levels
of abstraction. Limiting factors for large-scale mixed-mode
simulation are the speed of sequential simulation software, the relatively
high cost, and the low flexibility of hardware accelerators.
With the growing availability of powerful parallel processing
machines, parallel co-simulation is a viable approach to speeding
up simulation of large systems. Furthermore, integration and
extensibility could be achieved using a parallel software simulation
backplane. |
Relevance
Claims
1
Relevance
To illustrate the feedback breaking mechanism with a barrier, Figure
1 shows two processes that comprise a communication cycle,
in which one is simulating a register reg and the other is a generic
process P. To break the feedback cycle, the first step is the identification
of the feedback register reg, which is replaced with a barrier
B process. This process has explicit control of its input and output
communication.
To illustrate the feedback breaking mechanism with a barrier, Figure
1 shows two processes that comprise a communication cycle,
in which one is simulating a register reg and the other is a generic
process P. To break the feedback cycle, the first step is the identification
of the feedback register reg, which is replaced with a barrier
B process. This process has explicit control of its input and output
communication.
Claim Chart
All
2
Relevance
Optimistic scheduling is used in the Xmewarp [ I l l algorithm.
Such an algorithm allows the local time of a given process to be
increased beyond the local time of its input processes. In so doing,
it is possible to anticipate additional events. If events are rare, the
speculations may often be correct. If the prediction proves to be
wrong, the process would have to return to its previous correct
state.
The feedback resolution mechanism relies on using a burrier,
which is simulated according to the value of the associated register
state as well as the type of registers used in the design.
In the input phase of barrier B, the outputs of process P are taken
into account. With output opened, barrier B uses the values
received from the process P to update its inputs and internal states
for the next cycle.
Optimistic scheduling is used in the Xmewarp [ I l l algorithm.
Such an algorithm allows the local time of a given process to be
increased beyond the local time of its input processes. In so doing,
it is possible to anticipate additional events. If events are rare, the
speculations may often be correct. If the prediction proves to be
wrong, the process would have to return to its previous correct
state.
The feedback resolution mechanism relies on using a burrier,
which is simulated according to the value of the associated register
state as well as the type of registers used in the design.
In the input phase of barrier B, the outputs of process P are taken
into account. With output opened, barrier B uses the values
received from the process P to update its inputs and internal states
for the next cycle.
Claim Chart
All
3
Relevance
This strategy introduces overhead on message traffic. Deadlock
recovery is based on a two-phase scheme in which simulation proceeds
until it is blocked. When blocking is detected, a recovery
phase resolves the deadlock.
This strategy introduces overhead on message traffic. Deadlock
recovery is based on a two-phase scheme in which simulation proceeds
until it is blocked. When blocking is detected, a recovery
phase resolves the deadlock.
Claim Chart
All
4
Relevance
To achieve input updating
without rollback, time is allowed to proceed for the interval of one
inactive clock interval as if time were stretched. This clock interval
was simulated during the phase in which the barrier was closed and
inputs kept constant.
To achieve input updating
without rollback, time is allowed to proceed for the interval of one
inactive clock interval as if time were stretched. This clock interval
was simulated during the phase in which the barrier was closed and
inputs kept constant.
Claim Chart
All
5
Relevance
The resulting parallel simulation
backplane is capable of concurrently simulating systems at circuit,
switch, gate, RTL and behavioral levels. We
The resulting parallel simulation
backplane is capable of concurrently simulating systems at circuit,
switch, gate, RTL and behavioral levels. We
Claim Chart
All
6
Relevance
To achieve input updating
without rollback, time is allowed to proceed for the interval of one
inactive clock interval as if time were stretched. This clock interval
was simulated during the phase in which the barrier was closed and
inputs kept constant.
To achieve input updating
without rollback, time is allowed to proceed for the interval of one
inactive clock interval as if time were stretched. This clock interval
was simulated during the phase in which the barrier was closed and
inputs kept constant.
Claim Chart
All
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