Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

All

Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."

Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."

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Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”

Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”

All

Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”

Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”

Some

Page 4, Para 3: "Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY."

Page 4, Para 3: "Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY."

Some

Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

All

Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."

Page 3, Col 1, Para 2: "...The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forwardbiased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to reverse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output."

All

Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”

Abstract: “Here we report a bottom-up approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-deÞned semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale Þeld-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been conÞgured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.”

All

Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”

Page 3, Col. 1, Para 2: The reference describes realizing logic gates using crossbar arrays and further interconnection of these logic gates to achieve more complex computational functionalities. “The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY.”

Some

Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

Figure 3 illustrates a circuit implementation using nanoscale crossbar array logic for achieving a mathematical computation. Page 4, Col 2, Para 1: "Importantly, the data summarized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices."

All