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ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY

Sub-classifications for 711
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ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM711/0010000
 
Addressing extended or expanded memory711/0020000
 
Addressing cache memories711/0030000
 
Dynamic-type storage device (e.g., disk, tape, drum)711/0040000
 
For multiple memory modules (e.g., banks, interleaved memory)711/0050000
 
Virtual machine memory addressing711/0060000
 
STORAGE ACCESSING AND CONTROL711/1000000
 
Specific memory composition711/1010000
 
Solid-state read only memory (ROM)711/1020000
 
Programmable read only memory (PROM, EEPROM, etc.)711/1030001
 
Solid-state random access memory (RAM)711/1040000
 
Dynamic random access memory711/1050000
 
Refresh scheduling711/1060000
 
Ferrite core711/1070000
 
Content addressable memory (CAM)711/1080000
 
Shift register memory711/1090000
 
Circulating memory711/1100000
 
Accessing dynamic storage device711/1110000
 
Direct access storage device (DASD)711/1120000
 
Caching711/1130000
 
Arrayed (e.g., RAIDs)711/1140001
 
Detachable memory711/1150000
 
Bubble memory711/1160000
 
Hierarchical memories711/1170000
 
Caching711/1180000
 
Multiple caches711/1190000
 
Parallel caches711/1200000
 
Private caches711/1210000
 
Hierarchical caches711/1220001
 
User data cache and instruction data cache711/1230000
 
Cross-interrogating711/1240000
 
Instruction data cache711/1250000
 
User data cache711/1260000
 
Interleaved711/1270000
 
Associative711/1280000
 
Partitioned cache711/1290000
 
Shared cache711/1300000
 
Multiport cache711/1310000
 
Stack cache711/1320000
 
Entry replacement strategy711/1330000
 
Combined replacement modes711/1340000
 
Cache flushing711/1350000
 
Least recently used711/1360000
 
Look-ahead711/1370001
 
Cache bypassing711/1380000
 
No-cache flags711/1390000
 
Cache pipelining711/1400000
 
Coherency711/1410000
 
Write-through711/1420000
 
Write-back711/1430000
 
Cache status data bit711/1440000
 
Access control bit711/1450000
 
Snooping711/1460000
 
Shared memory area711/1470000
 
Plural shared memories711/1480000
 
Multiport memory711/1490000
 
Simultaneous access regulation711/1500000
 
Prioritized access regulation711/1510000
 
Memory access blocking711/1520000
 
Shared memory partitioning711/1530000
 
Control technique711/1540000
 
Read-modify-write (RMW)711/1550000
 
Status storage711/1560000
 
Interleaving711/1570000
 
Prioritizing711/1580000
 
Entry replacement strategy711/1590000
 
Least recently used (LRU)711/1600000
 
Archiving711/1610000
 
Backup711/1620000
 
Access limiting711/1630000
 
With password or key711/1640000
 
Internal relocation711/1650000
 
Resetting711/1660000
 
Access timing711/1670000
 
Concurrent accessing711/1680000
 
Memory access pipelining711/1690000
 
Memory configuring711/1700003
 
Based on data size711/1710000
 
Based on component size711/1720000
 
Memory partitioning711/1730000
 
ADDRESS FORMATION711/2000000
 
Slip control, misaligning, boundary alignment711/2010000
 
Address mapping (e.g., conversion, translation)711/2020000
 
Virtual addressing711/2030000
 
Predicting, look-ahead711/2040000
 
Directories and tables (e.g., DLAT, TLB)711/2050000
 
Translation tables (e.g., segment and page table or map)711/2060000
 
Directory tables (e.g., DLAT, TLB)711/2070000
 
Segment or page table descriptor711/2080000
 
Including plural logical address spaces, pages, segments, blocks711/2090000
 
Resolving conflict, coherency, or synonym problem711/2100000
 
Address multiplexing or address bus manipulation711/2110000
 
Varying address bit-length or size711/2120000
 
Generating prefetch, look-ahead, jump, or predictive address711/2130000
 
Operand address generation711/2140000
 
In response to microinstruction711/2150000
 
Hashing711/2160000
 
Generating a particular pattern/sequence of addresses711/2170000
 
Sequential addresses generation711/2180000
 
Incrementing, decrementing, or shifting circuitry711/2190000
 
Combining two or more values to create address711/2200000
 
Using table711/2210000
 
FOREIGN ART COLLECTION7110
 
CLASS-RELATED FOREIGN DOCUMENTS711/FOR0000
 
ACCESSING, ADDRESSING OR ALLOCATING WITHIN MEMORY SYSTEMS OR ARCHITECTURES (EPO)711/E120010
 
Addressing or allocation; relocation (EPO)711/E120020
 
With multidimensional access, e.g., row/column, matrix, etc. (EPO)711/E120030
 
With look-ahead addressing means (EPO)711/E120040
 
User address space allocation, e.g., contiguous or noncontiguous base addressing, etc. (EPO)711/E120050
 
Free address space management (EPO)711/E120060
 
In block-addressed memory (EPO)711/E120070
 
In block-erasable memory, e.g., flash memory, etc. (EPO)711/E120080
 
Garbage collection, i.e., reclamation of unreferenced memory (EPO)711/E120090
 
Using reference counting (EPO)711/E120100
 
Incremental or concurrent garbage collection, e.g., in real-time systems, etc. (EPO)711/E120110
 
Generational garbage collection (EPO)711/E120120
 
Multiple users address space allocation, e.g., using different base addresses, etc. (EPO)711/E120130
 
Using tables or multilevel address translation means (EPO)711/E120140
 
Addressing variable-length words or parts of words (EPO)711/E120150
 
In hierarchically structured memory systems, e.g., virtual memory systems, etc. (EPO)711/E120160
 
Addressing of memory level in which access to desired data or data block requires associative addressing means, e.g., cache, etc. (EPO)711/E120170
 
Using pseudo-associative means, e.g., set-associative, hashing, etc. (EPO)711/E120180
 
For peripheral storage systems, e.g., disc cache, etc. (EPO)711/E120190
 
With dedicated cache, e.g., instruction or stack, etc. (EPO)711/E120200
 
Using selective caching, e.g., bypass, partial write, etc. (EPO)711/E120210
 
Using clearing, invalidating, or resetting means (EPO)711/E120220
 
Multi-user, multiprocessor, multiprocessing cache systems (EPO)711/E120230
 
With multilevel cache hierarchies (EPO)711/E120240
 
With a network or matrix configuration (EPO)711/E120250
 
Cache consistency protocols (EPO)711/E120260
 
Using directory methods (EPO)711/E120270
 
Copy directories (EPO)711/E120280
 
Associative directories (EPO)711/E120290
 
Distributed directories, e.g., linked lists of caches, etc. (EPO)711/E120300
 
Limited pointers directories; state-only directories without pointers (EPO)711/E120310
 
With concurrent directory accessing, i.e., handling multiple concurrent coherency transactions (EPO)711/E120320
 
Using a bus scheme, e.g., with bus monitoring or watching means, etc. (EPO)711/E120330
 
In combination with broadcast means, e.g., for invalidation or updating, etc. (EPO)711/E120340
 
For main memory peripheral accesses, e.g., I/O or DMA, etc. (EPO)711/E120350
 
With software control, e.g., non-cacheable data, etc. (EPO)711/E120360
 
With cache invalidating means (EPO)711/E120370
 
With shared cache (EPO)711/E120380
 
For multiprocessing or multitasking (EPO)711/E120390
 
With main memory updating (EPO)711/E120400
 
Organization and technology of caches (EPO)711/E120410
 
Of parts of caches, e.g., directory or tag array, etc. (EPO)711/E120420
 
With plurality of cache hierarchy levels (EPO)711/E120430
 
Multiple simultaneous or quasi-simultaneous cache accessing (EPO)711/E120440
 
Cache with multiple tag or data arrays being simultaneously accessible (EPO)711/E120450
 
Partitioned cache, e.g., separate instruction and operand caches, etc. (EPO)711/E120460
 
Cache with interleaved addressing (EPO)711/E120470
 
Cache with multi-port tag or data arrays (EPO)711/E120480
 
Overlapped cache accessing, e.g., pipeline, etc. (EPO)711/E120490
 
By multiple requestors (EPO)711/E120500
 
With reload from main memory (EPO)711/E120510
 
Cache access modes (EPO)711/E120520
 
Burst mode (EPO)711/E120530
 
Page mode (EPO)711/E120540
 
Parallel mode, e.g., in parallel with main memory or CPU, etc. (EPO)711/E120550
 
Variable-length word access (EPO)711/E120560
 
With pre-fetch (EPO)711/E120570
 
Address translation (EPO)711/E120580
 
Using page tables, e.g., page table structures, etc. (EPO)711/E120590
 
Involving hashing techniques, e.g., inverted page tables, etc. (EPO)711/E120600
 
Using associative or pseudo-associative address translation means, e.g., translation look-aside buffer (TLB), address translation buffer (ATB), address cache, etc. (EPO)711/E120610
 
Associated with data cache (EPO)711/E120620
 
Data cache being concurrently physically addressed (EPO)711/E120630
 
Data cache being concurrently virtually addressed (EPO)711/E120640
 
For multiple virtual address spaces, e.g., segmentation, etc. (EPO)711/E120650
 
Decentralized address translation, e.g., in distributed shared memory systems, etc. (EPO)711/E120660
 
For peripheral accesses to main memory, e.g., DMA, etc. (EPO)711/E120670
 
For multiple virtual address spaces, e.g., segmentation, etc. (EPO)711/E120680
 
Replacement control (EPO)711/E120690
 
Using a replacement algorithm (EPO)711/E120700
 
Of the least frequently used type, e.g., with individual count value, etc. (EPO)711/E120710
 
With age list, e.g., queue, MRU-LRU list, etc. (EPO)711/E120720
 
Being minimized, e.g., nonMRU, etc. (EPO)711/E120730
 
Being generated by decoding array or storage (EPO)711/E120740
 
With special data handling, e.g., priority of data or instructions, pinning, errors, etc. (EPO)711/E120750
 
Using additional replacement algorithm (EPO)711/E120760
 
Adapted to multidimensional cache systems, e.g., set-associative, multi-cache, multi-set, or multilevel, etc. (EPO)711/E120770
 
Addressing physical block of locations, e.g., base addressing, module addressing, memory dedication, etc. (EPO)711/E120780
 
Interleaved addressing (EPO)711/E120790
 
Address space extension (EPO)711/E120800
 
For memory modules (EPO)711/E120810
 
For I/O modules, e.g., memory mapped I/O, etc. (EPO)711/E120820
 
Combination of memories, e.g., ROM and RAM, etc., to permit replacement or supplementing of words in one module by words in another module (EPO)711/E120830
 
Configuration or reconfiguration (EPO)711/E120840
 
With centralized address assignment (EPO)711/E120850
 
And decentralized selection (EPO)711/E120860
 
With decentralized address assignment (EPO)711/E120870
 
Address being position dependent (EPO)711/E120880
 
With feedback, e.g., presence or absence of unit detected by addressing, overflow detection, etc. (EPO)711/E120890
 
Multi-configuration, e.g., local and global addressing, etc. (EPO)711/E120900
 
Protection against unauthorized use of memory (EPO)711/E120910
 
By using cryptography (EPO)711/E120920
 
By checking subject access rights (EPO)711/E120930
 
Key-lock mechanism (EPO)711/E120940
 
In virtual system, e.g., with translation means, etc. (EPO)711/E120950
 
Using access table, e.g., matrix or list, etc. (EPO)711/E120960
 
In hierarchical protection system, e.g., privilege levels, memory rings, etc. (EPO)711/E120970
 
By checking object accessibility, e.g., type of access defined by the memory independently of subject rights, etc. (EPO)711/E120980
 
Protection being physical, e.g., cell, word, block, etc. (EPO)711/E120990
 
For module or part of module (EPO)711/E121000
 
For range (EPO)711/E121010
 
Protection being virtual, e.g., for virtual blocks or segments before translation mechanism, etc. (EPO)711/E121020
 
Protection against loss of memory contents (EPO)711/E121030