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APPLICATION LIST|ARCHIVED APPLICATIONS|US PATENT CLASSIFICATIONS

ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT

Sub-classifications for 710

Classifications	Code	Applications

INPUT/OUTPUT DATA PROCESSING	710/001000	0

Input/Output expansion	710/002000	0

Input/Output addressing	710/003000	0

Address data transfer	710/004000	0

Input/Output command process	710/005000	0

Operation scheduling	710/006000	0

Concurrently performing Input/Output operation and other operation unrelated to Input/Output	710/007000	0

Peripheral configuration	710/008000	1

Address assignment	710/009000	0

Configuration initialization	710/010000	0

Protocol selection	710/011000	0

As input or output	710/012000	0

By detachable memory	710/013000	0

Mode selection	710/014000	0

Peripheral monitoring	710/015000	0

Characteristic discrimination	710/016000	0

Availability monitoring	710/017000	0

Activity monitoring	710/018000	0

Status updating	710/019000	0

Concurrent Input/Output processing and data transfer	710/020000	0

Concurrent data transferring	710/021000	0

Direct Memory Accessing (DMA)	710/022000	0

Programmed control memory accessing	710/023000	0

By command chaining	710/024000	0

Timing	710/025000	0

Using addressing	710/026000	0

Via separate bus	710/027000	0

With access regulating	710/028000	0

Flow controlling	710/029000	0

Frame forming	710/030000	0

Transfer direction selection	710/031000	0

Transfer termination	710/032000	0

Data transfer specifying	710/033000	0

Transferred data counting	710/034000	0

Burst data transfer	710/035000	0

Input/Output access regulation	710/036000	0

Access dedication	710/037000	0

Path selection	710/038000	0

Access request queuing	710/039000	0

Access prioritization	710/040000	0

Dynamic	710/041000	0

Group	710/042000	0

Physical position	710/043000	0

Prioritized polling	710/044000	0

Time-slot accessing	710/045000	0

Input/Output polling	710/046000	0

Polled interrupt	710/047000	0

Input/Output interrupting	710/048000	0

Masking	710/049000	0

Vectored	710/050000	0

Accessing via a multiplexer	710/051000	0

Input/Output data buffering	710/052000	0

Alternately filling or emptying buffers	710/053000	0

Queue content modification	710/054000	0

Contents validation	710/055000	0

Buffer space allocation or deallocation	710/056000	0

Fullness indication	710/057000	0

Input/Output process timing	710/058000	0

Processing suspension	710/059000	0

Transfer rate regulation	710/060000	0

Synchronous data transfer	710/061000	0

Peripheral adapting	710/062000	0

Universal	710/063000	0

Via common units and peripheral-specific units	710/064000	0

Input/Output data modification	710/065000	0

Width conversion	710/066000	0

Keystroke interpretation	710/067000	0

Data compression and expansion	710/068000	0

Analog-to-digital or digital-to-analog	710/069000	0

Digital-to-digital	710/070000	0

Serial-to-parallel or parallel-to-serial	710/071000	0

Application-specific peripheral adapting	710/072000	0

For user input device	710/073000	0

For data storage device	710/074000	0

INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)	710/100000	0

Bus expansion or extension	710/300000	0

Card insertion	710/301000	0

Hot insertion	710/302000	0

Docking station	710/303000	0

Hot docking	710/304000	0

System configuring	710/104000	0

Protocol	710/105000	0

Using transmitter and receiver	710/106000	0

Bus access regulation	710/107000	0

Bus locking	710/108000	0

Bus polling	710/109000	0

Bus master/slave controlling	710/110000	0

Rotational prioritizing (i.e., round robin)	710/111000	0

Bus request queuing	710/112000	0

Centralized bus arbitration	710/113000	0

Static bus prioritization	710/114000	0

Physical position bus prioritization	710/115000	0

Dynamic bus prioritization	710/116000	0

Time-slotted bus accessing	710/117000	0

Delay reduction	710/118000	0

Decentralized bus arbitration	710/119000	0

Hierarchical or multilevel accessing	710/120000	0

Static bus prioritization	710/121000	0

Physical position bus prioritization	710/122000	0

Dynamic bus prioritization	710/123000	0

Time-slotted bus accessing	710/124000	0

Delay reduction	710/125000	0

Bus interface architecture	710/305000	0

Bus bridge	710/306000	0

Variable or multiple bus width	710/307000	0

Direct memory access (e.g., DMA)	710/308000	0

Arbitration	710/309000	0

Buffer or que control	710/310000	0

Intelligent bridge	710/311000	0

Multiple bridges	710/312000	0

Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.)	710/313000	0

Common protocol (e.g., PCI to PCI)	710/314000	0

Different protocol (e.g., PCI to ISA)	710/315000	0

Path selecting switch	710/316000	0

Crossbar	710/317000	0

ACCESS LOCKING	710/200000	0

ACCESS POLLING	710/220000	0

ACCESS ARBITRATING	710/240000	1

Centralized arbitrating	710/241000	0

Decentralized arbitrating	710/242000	0

Hierarchical or multilevel arbitrating	710/243000	0

Access prioritizing	710/244000	0

INTERRUPT PROCESSING	710/260000	0

Multimode interrupt processing	710/261000	0

Interrupt inhibiting or masking	710/262000	0

Interrupt queuing	710/263000	0

Interrupt prioritizing	710/264000	0

Variable	710/265000	0

Programmable interrupt processing	710/266000	0

Processor status	710/267000	0

Source or destination identifier	710/268000	0

Handling vector	710/269000	0

FOREIGN ART COLLECTION	710	0

CLASS-RELATED FOREIGN DOCUMENTS	710/FOR000	0