1

An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:at least one memory device; and

at least one packet processor uniquely associated with each of the at least one memory device, and

the at least one packet processor adapted to provide high speed packet switched serial interface for read and write access to the at least one memory device by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication, and

further the at least one packet processor adapted to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface,

wherein the at least one memory device and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible,

such that the high-speed packet switched serial interface transfers the serialized protocol packet, to an external device configured for read and write access to the at least one memory device using a serial packetized protocol.

View Prior Art for Claim

2

The apparatus of Claim 1 further comprising:at least one processor core uniquely associated with at least one packet processor adapted to provide high speed packet switched serial interface for read and write access by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication, and

at least one switch interface operably connected to each packet processor and to the at least one external port and co-located on the semiconductor die package and adapted to mediate serial packetized communications among the packet processors and the at least one external port.

View Prior Art for Claim

3

The apparatus of Claim 1 wherein the at least packet one processor is implemented as an on-the-fly programmable bit stream processor.

View Prior Art for Claim

4

The apparatus of Claim 2 wherein the at least one switch is implemented as an on-the-fly programmable bit stream processor.

View Prior Art for Claim

5

The apparatus of Claim 2 wherein the high-speed packet switched serial interface is further adapted to transfer data from and to an external packet-switched network, in addition to an external device.

View Prior Art for Claim

6

The apparatus of Claim 5 wherein the high-speed packet switched serial interface is an Ethernet interface and the packet processor is adopted to support Ethernet protocol.

View Prior Art for Claim

7

The apparatus of Claim 6 wherein the external packet-switched network is the Internet.

View Prior Art for Claim

8

A method of implementing a computing and communication chip architecture for integrated circuitry, comprising:providing a semiconductor die package having co-located thereon at least one memory device with at least one packet processor uniquely associated with each of the at least one memory device, the at least one packet processor adapted to provide a high-speed packet switched serial interface for memory access to the at least memory device by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication, and

further the at least one packet processor adapted to translate between multiple serialized protocols communicated over the high-speed packet switched serial interface,

utilizing the high-speed packet switched serial interface to transfer the serialized packet to an external device configured to read and write data form the at least one memory device using a serial packetized protocol.

View Prior Art for Claim

9

The method of Claim 8 further comprising:providing least a processor core uniquely associated with at least one packet processor adapted to provide high speed packet switched serial interface for read and write access by encapsulating and decapsulating address, data and control information, using a packetized protocol for switched serial communication,

providing at least one switch interface operably connected to each packet processor and to the at least one external port and co-located on the semiconductor die package; and

utilizing the at least one switch interface to mediate serial packetized communications among the packet processors and the at least one external port.

View Prior Art for Claim

10

The method of Claim 8 wherein the packet processor is implemented as an on-the-fly programmable bit stream processor.

View Prior Art for Claim