Pre-Grant Publication Number: 20110035571
On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol
Filing Date: October 25, 2010Priority Date: February 04, 2008
Inventors: VISWA SHARMA
Assignee(s): PSIMAST, INC
Current U.S. Classification: 712, 712/038000, 712/E09003
View Prior Art for Claim 00005
The apparatus of Claim 2 wherein the high-speed packet switched serial interface is further adapted to transfer data from and to an external packet-switched network, in addition to an external device.
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