Pre-Grant Publication Number: 20090106489
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Prior Art (3)
Patent/Application # 20040143613
Description
..having a register array..plurality of operands, a pipeline for executing..instructions with a plurality of stages, ..having a stage register, data input registers..(which) form the first stage register of the pipeline. An input port loads..into one..data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port,and the output..provided to the data input registers, such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers from a respective bypass-register...
Title IBM Journal of Research and Development
ISBN
Description
Article describing a multiply-add-fused (MAF) unit.
Patent/Application # 4969118
Description
Processor floating point unit - provides for simultaneous multiply and add operations
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