Pre-Grant Publication Number: 20090106489
Filing Date: October 22, 2007
Inventors: Chun-Yu Chen, Shu-Ming Liu
Assignee(s): Wenshine Technology LTD
Current U.S. Classification: 711, 711/110000, 711/E12016
View Prior Art for Claim 00002
The data processing apparatus according to Claim 1, wherein the registers further comprises a second register, and the data processing apparatus further comprises:a logic unit, for providing the operational data of the first register to the second register in response to a second control signal, and then providing the first backup operand stored in the shadow register to the first register. Annotations(0)
Patent/Application # 4969118
Processor floating point unit - provides for simultaneous multiply and add operations
Title IBM Journal of Research and Development
Article describing a multiply-add-fused (MAF) unit.
Patent/Application # 20040143613
..having a register array..plurality of operands, a pipeline for executing..instructions with a plurality of stages, ..having a stage register, data input registers..(which) form the first stage register of the pipeline. An input port loads..into one..data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port,and the output..provided to the data input registers, such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers from a respective bypass-register...