Pre-Grant Publication Number: 20090106489
Filing Date: October 22, 2007
Inventors: Chun-Yu Chen, Shu-Ming Liu
Assignee(s): Wenshine Technology LTD
Current U.S. Classification: 711, 711/110000, 711/E12016
View Prior Art for Claim 00005
The data processing apparatus according to Claim 1, wherein the arithmetic operation command is a multiply-accumulate (MLA) command, and the operation unit performs at least a multiplying-operation and at least an accumulating-operation on the operands.
Submitted by: Diane WillisLast updated: almost 4 years ago
Patent/Application # 4969118
Description
Processor floating point unit - provides for simultaneous multiply and add operations
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Submitted by: Diane WillisLast updated: almost 4 years ago
Title IBM Journal of Research and Development
ISBN
Description
Article describing a multiply-add-fused (MAF) unit.
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