A data processing apparatus comprising a register bank, a shadow register and an arithmetic operation unit is provided. The register bank comprises a number of registers for respectively storing a number of operands, respectively, wherein the registers are n-bit registers, and n is a nature number. The shadow register is for storing first backup operand for making a backup of a first operand, which is stored in a first register among the registers in response to first control signal. The arithmetic operation unit is for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command.