Pre-Grant Publication Number: 20080104325
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to apply to slower anf faster cache memories.
Also, I'm trying to understand the invention here, how this is different from what has already been done. Is it the idea of a 'monitor'?
Still, it is common for a programmer to explicitly place a lock and data together with the knowledge that common bus hardware will pull the data into a more local cache at the time of the lock acquisition. Since they say "not as a part of the request from the consumer", perhaps it is this in combination with the monitor that is their aim at uniqueness? In my scenario the next data to be consumed (or probably reference to it anyway) would be effectively prefetched by hardware due to consumer request activity once they started trying to get the queue's lock.
It would be useful if they had more explicit description of how this is unique from the current art in cache coherency protocols/implementations/theory for multicore / multiprocessor machines, MESI implementations, bus snooping, cache line prefetching, cache line replacement and such. Their background talks about not wanting to rely on microarchitectural details, so maybe this monitor is meant to be at a higher logical level or that is the patent attorney generalizing the application as much as possible. Nevertheless It seems conceptually like something cpu/cache hardware today is liable to do today and into which research would have been done possibly as far back as the mid/late 80's.
And to go back to the original comment, this really does describe HSM, just in the cpu/cache space instead of in the SAN space.