Pre-Grant Publication Number: 20070174746
Filing Date: December 20, 2005
Inventors: Juerg Haefliger, William Bruckert, James Klecka
Assignee(s): HEWLETT PACKARD COMPANY
Current U.S. Classification: 714, 714/721000
View Prior Art for Claim 00002
The method of Claim 1 further comprising: determining a first voltage value where the plural processors exhibit anomalies while executing instructions; and determining a second voltage value where the plural processors exhibit failures while executing instructions. Annotations(1)
A codesign methodology incorporates timing speculation into a low-power micropocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths
Title Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Another description of the RAZOR architecture. Instead of a plurality of processors, it has one with a plurality of latches. This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep.
Title A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock-Generator for Variable-Load Appl
This paper describes a processor, controller, and machine readable description for processor tuning. It is tuning clock speed at constant voltage, but this would be commonly recognized to pertain to voltage tuning at constant speed.