A codesign methodology incorporates timing speculation into a low-power micropocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths

Another description of the RAZOR architecture. Instead of a plurality of processors, it has one with a plurality of latches. This is better in some ways than the proposed architecture (since the overhead is smaller) , and it could be argued it is a small step, clear to those educated in the art, between 1 processors with two sets of latches, and two processors running in lockstep.

This paper describes a processor, controller, and machine readable description for processor tuning. It is tuning clock speed at constant voltage, but this would be commonly recognized to pertain to voltage tuning at constant speed.